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| author | Peter Geis <[email protected]> | 2022-04-29 07:52:51 -0400 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2022-05-01 15:03:01 +0200 |
| commit | 5859b5a9c3ac92d831bed164374cb837519524ad (patch) | |
| tree | f33e409b049cd0fced5309e4f66b51ad38188128 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | dcc8c66bef79befa6c9ebe7d7d62b0ce66983c20 (diff) | |
arm64: dts: rockchip: add SoQuartz CM4IO dts
This is the initial SoQuartz SoM device tree on a CM4IO carrier board.
This board outputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 (OTG/Host shared)
PCIe 2.0 x1
HDMI (HDMI Port 0)
eDP (HDMI Port 1)
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI NOR Flash (Not placed)
PI-40 compatible pin header
Signed-off-by: Peter Geis <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions