diff options
| author | Nicolas Ferre <[email protected]> | 2013-05-14 03:00:16 +0000 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2013-05-14 13:04:02 -0700 |
| commit | 581df9e1944194bfcabc57e1efae79b0fe171d6f (patch) | |
| tree | c9965f5d51aaadee4bbaf3b1608876ac743015b3 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | faff57a92ba1d7247c5e86ecea2886d2c9d54507 (diff) | |
net/macb: fix ISR clear-on-write behavior only for some SoC
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <[email protected]>
Signed-off-by: Nicolas Ferre <[email protected]>
Tested-by: Hein Tibosch <[email protected]>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions