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| author | Sylwester Nawrocki <[email protected]> | 2013-03-21 14:22:34 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2013-04-04 20:23:53 -0300 |
| commit | 439797980af4bddfc2b86a44ddb573c5e48a1fcc (patch) | |
| tree | 3cee3905e065b5c0fd5715e7ff32b26bd779194a /tools/perf/scripts/python/check-perf-trace.py | |
| parent | e90ad659cde4d11ccbc935adcfe018799afcc22d (diff) | |
[media] exynos4-is: Correct input DMA YUV order configuration
This patch fixes erroneous setup of the YUV order caused by not
clearing FIMC_REG_MSCTRL_ORDER422_MASK bit field before setting
proper FIMC_REG_MSCTRL_ORDER422 bits. This resulted in false
colors for YUYV, YVYU, UYVY, VYUY color formats, depending in
what sequence those were configured by user space.
YUV order definitions are corrected so that following convention
is used:
| byte3 | byte2 | byte1 | byte0
-------+-------+-------+-------+------
YCBYCR | CR | Y | CB | Y
YCRYCB | CB | Y | CR | Y
CBYCRY | Y | CR | Y | CB
CRYCBY | Y | CB | Y | CR
Signed-off-by: Sylwester Nawrocki <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions