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authorChen-Yu Tsai <[email protected]>2019-01-25 11:23:11 +0800
committerMaxime Ripard <[email protected]>2019-01-25 10:43:07 +0100
commit437262c0db5de0f3d351592fe92b581dcaf91869 (patch)
treeebb0ee8af3f6bbdcab187233362d601485272669 /tools/perf/scripts/python/check-perf-trace.py
parentd027521497592773cd23d016d36975574d3452db (diff)
ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi
The display pipeline has the same structure, resources and connections on both the A23 and A33. The differences include: - compatible strings - extra clock, reset control, and IO region for SAT in the backend only found on the A33 - missing ch1 clock for the TCON However, while the A23 has the TCON ch1 clock defined in the CCU, and the channel 1 registers are available, it does not have any means to use channel 1 due to a lack of downstream encoders, and the enable bit for channel 1 is hard-wired to 0 (off). As the MIPI DSI output device is not officially documented, and there are no A23 reference devices to test it, it is not covered by this patch. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
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