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author | Biju Das <[email protected]> | 2022-03-15 14:26:38 +0000 |
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committer | Geert Uytterhoeven <[email protected]> | 2022-04-04 11:00:51 +0200 |
commit | 3f285c301cd788164fa776e1f95458c56e68a6ee (patch) | |
tree | d5a75aa91b7f32cb2522d939b03843b0c07194df /tools/perf/scripts/python/check-perf-trace.py | |
parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) |
dt-bindings: power: renesas,rzg2l-sysc: Document RZ/G2UL SoC
Add DT binding documentation for SYSC controller found on RZ/G2UL SoC's.
SYSC controller found on the RZ/G2UL SoC is almost identical to one found
on the RZ/G2L SoC's only difference being that the RZ/G2UL has only CA55
core0 reset vector address configuration register.
Signed-off-by: Biju Das <[email protected]>
Reviewed-by: Lad Prabhakar <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions