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authorAndre Przywara <[email protected]>2022-03-17 16:23:48 +0000
committerJernej Skrabec <[email protected]>2022-04-06 22:27:40 +0200
commit335f57508a7a3220feb161400f0475e7f42be1b3 (patch)
treee62be53f45d44ac5a14080c4c71ddb16103e29fe /tools/perf/scripts/python/check-perf-trace.py
parent382e0d4f9ece6d1b282ac70c246bdc7be5edc053 (diff)
ARM: dts: suniv: F1C100: add SPI support
The F1C100 series contains two SPI controllers, and many boards use SPI0 for a SPI flash, as the BROM is able to boot from that. Describe the two controllers in the SoC .dtsi, and also add the PortC pins for SPI0, since this is where BROM looks at when trying to boot from the commonly used SPI flash. The SPI controller seems to be the same as in the H3 chips, but it lacks a separate mod clock. The manual says it's connected to AHB directly. We don't export that AHB clock directly, but can use the AHB *gate* clock as a clock source, since the SPI driver is not supposed to change the AHB frequency anyway. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Samuel Holland <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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