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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2021-07-19 09:58:39 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-07-19 11:22:23 +0200 |
| commit | 1b87d5bba32c1f25a12ba0625546e5375e3f998d (patch) | |
| tree | 95c3270e2432b8bdeaabf360b1633b2241e534bf /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 3b5c734592ade51fed3982bc840a830e066e668e (diff) | |
clk: renesas: r9a07g044: Add clock and reset entries for ADC
Add clock and reset entries for ADC block in CPG driver.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210719085840.21842-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions