diff options
| author | S.j. Wang <[email protected]> | 2019-04-04 09:40:56 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2019-04-05 09:54:03 +0700 |
| commit | 1997ee89f36da906efb8e700f1d08368c73883be (patch) | |
| tree | 4449b9f37eefa3171bf428ea23c720e069a3b874 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 2114171d9cce1a897bee394b06f6c224247f095c (diff) | |
ASoC: fsl_esai: Support synchronous mode
In ESAI synchronous mode, the clock is generated by Tx, So
we should always set registers of Tx which relate with the
bit clock and frame clock generation (TCCR, TCR, ECR), even
there is only Rx is working.
Signed-off-by: Shengjiu Wang <[email protected]>
Acked-by: Nicolin Chen <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions