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| author | Huacai Chen <[email protected]> | 2017-03-16 21:00:28 +0800 |
|---|---|---|
| committer | Ralf Baechle <[email protected]> | 2017-04-10 11:56:08 +0200 |
| commit | 17c99d9421695a0e0de18bf1e7091d859e20ec1d (patch) | |
| tree | b85ec6aa09ba082e12840be02bc2ea09fda28071 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | 294d62743754f1fefefccccb09f8deec48f00969 (diff) | |
MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.
Signed-off-by: Huacai Chen <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J . Hill <[email protected]>
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Cc: [email protected]
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions