diff options
| author | Alexander Shiyan <[email protected]> | 2014-04-03 14:50:00 -0700 |
|---|---|---|
| committer | Linus Torvalds <[email protected]> | 2014-04-03 16:21:21 -0700 |
| commit | 12de362108d5ec24cce1bbe520570dc8fdccca9c (patch) | |
| tree | 04de7d96005b26d239f376e587f8d3526d8e34c7 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | fb1bd9a22da3d0f2436ffa95fdc0382b89659288 (diff) | |
rtc: mc13xxx: change RTC validation scheme
Datasheet says: "When the VSRTC voltage drops to the range of 0.9 - 0.8V,
the RTCPORB reset signal is generated and the contents of the RTC will
be reset. <skip>. To inform the processor that the contents of the RTC
are no longer valid due to the reset, a timer reset interrupt function
is implemented with the RTCRSTI bit." This patch makes the RTC valid by
default until RTCRST interrupt occurs.
Signed-off-by: Alexander Shiyan <[email protected]>
Cc: Uwe Kleine-König <[email protected]>
Cc: Sascha Hauer <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions