diff options
| author | Shengjiu Wang <[email protected]> | 2022-10-28 15:03:47 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2022-10-28 12:58:19 +0100 |
| commit | 107d170dc46e14cfa575d1b995107ef2f2e51dfe (patch) | |
| tree | 19f93bd69dac774e82856a64d259a3db50ffe4c6 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | ce992ff38e1ed495be202c22d065b42c942e0475 (diff) | |
ASoC: fsl_xcvr: Add Counter registers
These counter registers are part of register list,
add them to complete the register map
- DMAC counter control registers
- Data path Timestamp counter register
- Data path bit counter register
- Data path bit count timestamp register
- Data path bit read timestamp register
Signed-off-by: Shengjiu Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions