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authorLucas De Marchi <[email protected]>2020-10-14 12:19:32 -0700
committerLucas De Marchi <[email protected]>2020-10-15 14:14:32 -0700
commit0dac17af0ab4e55b6b18a762141f255d3eea1e37 (patch)
tree92d4e33d076720baf28100508830f7ec40beea20 /tools/perf/scripts/python/check-perf-trace.py
parentb71b477d9414fda42126fd2c55c5e8fa09347433 (diff)
drm/i915/dg1: Enable DPLL for DG1
Add DG1 DPLL Enable register macro and use the macro to enable the correct DPLL based on PLL id. Although we use _MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys. While at it, fix coding style: wrong newlines and use if/else chain v2: Rewrite original patch from Aditya Swarup based on refactors upstream Bspec: 49443, 49206 Cc: Clinton Taylor <[email protected]> Cc: Matt Roper <[email protected]> Cc: Aditya Swarup <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Aditya Swarup <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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