diff options
| author | Martin Blumenstingl <[email protected]> | 2017-10-31 21:01:46 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2018-01-08 16:03:42 +0100 |
| commit | fda29dbac9e6604f8eeb660953a2bef360514dc7 (patch) | |
| tree | ae63afb952771ebc0e318d554fb42e4557faf8d6 /tools/perf/scripts/python/call-graph-from-sql.py | |
| parent | b9a3589332c2a25fb7edad25a26fcaada3209126 (diff) | |
iio: adc: meson-saradc: fix the clock frequency on Meson8 and Meson8b
GX SoCs use a 1.2 MHz ADC clock, while the older SoCs use a 1.14 MHz
clock.
A comment in the driver from Amlogic's GPL kernel says that it's
running at 1.28 MHz. However, it's actually programming a divider of
20 + 1. With a XTAL clock of 24 MHz this results in a frequency of
1.14 MHz. (their calculation might be based on a 27 MHz XTAL clock,
but this is not what we have on the Meson8 and Meson8b SoCs).
The ADC was still working with the 1.2MHz clock. In my own tests I did
not see a difference between 1.2 and 1.14 MHz (regardless of the clock
frequency used, the ADC results were identical).
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jonathan Cameron <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-sql.py')
0 files changed, 0 insertions, 0 deletions