Merge tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx into next/dt

Merge "NXP LPC32xx device tree updates for v4.7" from Vladimir Zapolskiy:

This includes a few functional changes:
* new representation of MIC, SIC1 and SIC2 interrupt controllers,
* disabled by default SPI1, SPI2, SSP0 and SSP1 SPI controllers in
  shared lpc32xx.dtsi file,
* added clock sources for SPI1 and SPI2,
* set default clock rate of HCLK PLL to main osc rate multiplied by 16.

Also there are some non-functional changes:
* flatten board DTS files by exploiting device node labels,
* add 'partitions' device node for NAND SLC / MTD OF,
* correct Atmel vendor prefix to describe on board AT24 EEPROMs,
* rename board DTS files by adding SoC name prefix.

Since now DTS files of LPC32xx boards match "^lpc32[2345]0-" pattern.

* tag 'lpc32xx-dt-4.7' of git://github.com/vzapolskiy/linux-lpc32xx:
  ARM: dts: lpc32xx: phy3250: add SoC name prefix to board dts file
  ARM: dts: lpc32xx: phy3250: add NAND partitions device node
  ARM: dts: lpc32xx: phy3250: avoid extension of device nodes by absolute path
  ARM: dts: lpc32xx: ea3250: add SoC name prefix to board dts file
  ARM: dts: lpc32xx: ea3250: fix Atmel at24 eeprom vendor
  ARM: dts: lpc32xx: ea3250: add NAND partitions device node
  ARM: dts: lpc32xx: ea3250: avoid extension of device nodes by absolute path
  ARM: dts: lpc32xx: reparent SIC1 and SIC2 interrupts from MIC
  dt-bindings: interrupt-controllers: add description of SIC1 and SIC2
  ARM: dts: lpc32xx: disabled ssp0/spi1 & ssp1/spi2 by default
  ARM: dts: phy3250: enable ssp0
  ARM: dts: lpc32xx: add clock properties to spi nodes
  ARM: dts: lpc32xx: set default clock rate of HCLK PLL

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