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authorLinus Walleij <[email protected]>2015-05-19 10:55:14 -0600
committerGreg Kroah-Hartman <[email protected]>2015-05-24 11:12:08 -0700
commitd1839e68777316cc607d1d3f82579046ca945958 (patch)
tree0b02b9f0e59571e903e81d9984f42539220c61cb /tools/perf/scripts/python/bin
parent32398ef6f4745b2098d93f32e2c89e0286ab45fe (diff)
coresight: etm: retrieve and handle atclk
As can be seen from the datasheet of the CoreSight Components, DDI0401C A.1.1 the ETM has a clock signal apart from the AHB interconnect ("amba_pclk", that we're already handling) called ATCLK, ARM Trace Clock, that SoC implementers may provide from an entirely different clock source. So to model this correctly create an optional path for handling ATCLK alongside the PCLK so we don't break old platforms that only define PCLK ("amba_pclk") but still makes it possible for SoCs that have both clock signals (such as the DB8500) to fetch and prepare/enable/disable/ unprepare both clocks. The ATCLK is enabled and disabled using the runtime PM callbacks. Reviewed-by: Ulf Hansson <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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