diff options
| author | Roy Spliet <[email protected]> | 2012-01-09 15:23:07 +1000 |
|---|---|---|
| committer | Ben Skeggs <[email protected]> | 2012-03-13 17:07:50 +1000 |
| commit | c7c039fd31be82ecb8d48477955e76badd38141a (patch) | |
| tree | 0b527eba7fd021ce99c52d9f744d503d0919849c /tools/perf/scripts/python/bin | |
| parent | 03ddf04bdb9cc4cdf8edb231b78f031647498314 (diff) | |
drm/nouveau/pm: implement DDR2/DDR3/GDDR3/GDDR5 MR generation and validation
Roy Spliet:
- Implement according to specs
- Simplify
- Make array for mc latency registers
Martin Peres:
- squash and split all the commits from Roy
- rework following Ben Skeggs comments
- add a form of timings validation
- store the initial timings for later use
Ben Skeggs
- merge slightly modified tidy-up patch with this one
- remove perflvl-dropping logic for the moment
Signed-off-by: Roy Spliet <[email protected]>
Signed-off-by: Martin Peres <[email protected]>
Signed-off-by: Ben Skeggs <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions