clk: ingenic: Add .set_rate_hook() for PLL clocks

The set rate hook is called immediately after updating the clock
register but before the spinlock is released. This allows another
register to be updated alongside the main one, which is needed to
handle the I2S divider on some SoCs.

Signed-off-by: Aidan MacDonald <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Paul Cercueil <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions