arm64: dts: mt6795: Add complete CPU caches information

This SoC's AP subsystem has 8x Cortex-A53 CPUs, specifically,
four CPUs per cluster, with two CPU clusters.

Each CPU has:
 - A 32KB I-cache, 2-way set associative;
 - A 32KB D-cache, 4-way set associative.

Each cluster has a unified 1MB L2 cache, 16-way set associative.

With that in mind, add the appropriate properties needed to specify the
caches information for this SoC, which will now be correctly exported
to sysfs.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Matthias Brugger <[email protected]>

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