diff options
| author | Peter 'p2' De Schrijver <[email protected]> | 2010-12-20 14:05:07 -0600 |
|---|---|---|
| committer | Kevin Hilman <[email protected]> | 2010-12-21 14:45:51 -0800 |
| commit | c4236d2e7913d18d058a018f0d19473eb6a11a3c (patch) | |
| tree | b90600a00f6dd27eb03f7a278a5959a5f7d5b6a6 /tools/perf/scripts/python/bin | |
| parent | 458e999eb14a301d4176783c8fcb277f5d009b4e (diff) | |
OMAP3630: PM: Disable L2 cache while invalidating L2 cache
While coming out of MPU OSWR/OFF states, L2 controller is reseted.
The reset behavior is implementation specific as per ARMv7 TRM and
hence $L2 needs to be invalidated before it's use. Since the
AUXCTRL register is also reconfigured, disable L2 cache before
invalidating it and re-enables it afterwards. This is as per
Cortex-A8 ARM documentation.
Currently this is identified as being needed on OMAP3630 as the
disable/enable is done from "public side" while, on OMAP3430, this
is done in the "secure side".
Cc: Kevin Hilman <[email protected]>
Cc: Tony Lindgren <[email protected]>
Acked-by: Jean Pihet <[email protected]>
Acked-by: Santosh Shilimkar <[email protected]>
[[email protected]: ported to 2.6.37-rc2, added hooks to enable the logic only on 3630]
Signed-off-by: Nishanth Menon <[email protected]>
Signed-off-by: Eduardo Valentin <[email protected]>
Signed-off-by: Peter 'p2' De Schrijver <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions