diff options
| author | Nicolin Chen <[email protected]> | 2020-10-07 17:37:42 -0700 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2020-10-27 09:03:56 +0100 |
| commit | c14bea053775e0c79a6fdd2d1b5a1d9de4fbd7c7 (patch) | |
| tree | 4872268640f3b9647265c406eb45b6dea7c217c3 /tools/perf/scripts/python/bin | |
| parent | 3650b228f83adda7e5ee532e2b90429c03f7b9ec (diff) | |
memory: tegra: Correct la.reg address of seswr
According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
[23:16] of register at address 0x3e0 with a reset value of 0x80
at register 0x3e0, while bit-1 of register 0xb98 is for enable
bit of seswr.
Signed-off-by: Nicolin Chen <[email protected]>
Acked-by: Thierry Reding <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions