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| author | Athira Rajeev <[email protected]> | 2022-06-10 19:10:59 +0530 |
|---|---|---|
| committer | Michael Ellerman <[email protected]> | 2022-06-29 08:57:43 +1000 |
| commit | beebeecb47d3b93198fe46922fd4ba2af2090cdd (patch) | |
| tree | be2f95ba11b6fc8de4c28b194af6aa3d7d879845 /tools/perf/scripts/python/bin | |
| parent | dc431be3b54901744e84f5f94f0f0a2b5d36bb7f (diff) | |
selftests/powerpc/pmu: Add selftest for group constraint for MMCRA Sampling Mode field
Testcase for reserved bits in Monitor Mode Control Register A (MMCRA)
Random Sampling Mode (SM) value. As per Instruction Set
Architecture (ISA), the values 0x5, 0x9, 0xD, 0x19, 0x1D, 0x1A, 0x1E are
reserved for sampling mode field. Test that having these reserved bit
values should cause event_open to fail. Input event code in testcases
uses these sampling bits along with 401e0 (PM_MRK_INST_CMPL).
Signed-off-by: Athira Rajeev <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions