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authorSung Lee <[email protected]>2020-09-24 16:21:21 -0400
committerAlex Deucher <[email protected]>2020-10-05 15:17:13 -0400
commitb98ab70e748e54b6b53abc2a20380ceb01e421fc (patch)
treee9bd480289a0baf5e722cd7079b6e2eeca44954a /tools/perf/scripts/python/bin
parent5dff371a7351a7e9cbb06bca9e532db16594c053 (diff)
drm/amd/display: Hardcode 45W Bounding Box for DCN2.1 Diags
[WHY] Currently construction of clock limits gets skipped for diags. This logic would be useful to get tested in diags. [HOW] Copy existing states to clk_table such that update_bw_bounding_box logic gets used to fill the table. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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