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authorJames Liao <[email protected]>2015-07-10 16:39:32 +0800
committerStephen Boyd <[email protected]>2015-07-28 11:58:52 -0700
commitb3be457e5854e3095cd0be850058c765aaf467ab (patch)
tree427efcbd2d64d3d21b2642289c89f4e6b3142bc3 /tools/perf/scripts/python/bin
parent9783c0d98501aa146ff467916ab4b8830a655d7c (diff)
clk: mediatek: Fix PLL registers setting flow
Write postdiv and pcw settings at the same time for PLLs if postdiv and pcw settings are on the same register. This is need by PLLs such as MT8173 MMPLL and ARM*PLL. Signed-off-by: James Liao <[email protected]> Acked-by: Sascha Hauer <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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