diff options
| author | Borun Fu <[email protected]> | 2014-07-12 10:02:27 +0530 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2014-07-23 07:04:54 +0200 |
| commit | b04c5bd6fda54703e56f29569e4bca489d6c5a5c (patch) | |
| tree | 85e14146da8f4e50bf4f961c26312c190bee217d /tools/perf/scripts/python/bin | |
| parent | b55dd64720919ba8d6830fbaec9e779e4bdb0ae0 (diff) | |
drm/i915: Power gating display wells during i915_pm_suspend
On VLV, after i915_pm_suspend display power wells are staying
power ungated. So, after initiating mem sleep "echo mem > /sys/power/state"
Display is staing D0 State. There might be better way/place to power gate
these wells. Also, we need to make sure that if wells are power gated due to
DPMS OFF sequence, they need not be turned off by i915_pm_suspend again.
v2: Extracted helper for intel_crtc_disable and power gating CRTC power wells.
[Daniel]
Cc: Imre Deak <[email protected]>
Cc: Paulo Zanoni <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Jani Nikula <[email protected]>
Change-Id: I34c80da66aa24c423a5576c68aa1f3a8d0f43848
Signed-off-by: Borun Fu <[email protected]>
Signed-off-by: Sagar Kamble <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions