diff options
| author | Paul Kocialkowski <[email protected]> | 2022-05-25 20:02:57 +0100 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2022-07-08 15:02:22 +0100 |
| commit | af54b4f4c17f54e8c7c43fb34571bc361cfa4ab4 (patch) | |
| tree | 966506589f284e7fcd6a526fcb0ed79ac54d84ec /tools/perf/scripts/python/bin | |
| parent | 787d694677f0c8d76021c4d5ec2e55c256fd33b8 (diff) | |
media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
Signed-off-by: Paul Kocialkowski <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reported-by: kernel test robot <[email protected]>
Signed-off-by: Hans Verkuil <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions