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authorKonrad Dybcio <[email protected]>2023-11-20 13:12:53 +0100
committerBjorn Andersson <[email protected]>2023-12-07 08:37:45 -0800
commit94085049fdad7a36fe14dd55e72e712fe55d6bca (patch)
tree60c5058379fb1b1b51453793f59c6358e4ffc934 /tools/perf/scripts/python/bin
parent0ab1bef0b7c359e672cc2b8d51f0179cefa369fc (diff)
arm64: dts: qcom: sc7280: Fix up GPU SIDs
GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). On platforms that support it (in firmware), it is necessary to describe that link, or Adreno register access will hang the board. The current settings are functionally identical, *but* due to what is likely hardcoded security policies, the secure firmware rejects them, resulting in the board hanging. To avoid that, alter the settings such that SID 0 and 1 are described separately. Fixes: 96c471970b7b ("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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