diff options
| author | Ville Syrjälä <[email protected]> | 2013-12-09 18:54:14 +0200 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2013-12-11 23:52:14 +0100 |
| commit | 91dbe5fb77a2afea04a52b432cfb4529d72096d1 (patch) | |
| tree | b80650753f864604f18c9c2c758e3da6cd611fec /tools/perf/scripts/python/bin | |
| parent | b1c560d13d1aab194b467ca33d0be6ca6e829ee5 (diff) | |
drm/i915: Change N divider minimum from 3 to 2 for gen2
Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen.
The VBT mode is as follows:
0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa
The BIOS uses the following DPLL settings:
DPLL = 0x90020000
FP0 = 0x2140e
FP1 = 0x21207
We can't generate that pixel clock currently as we're limiting the N
divider to at least 3, whereas the BIOS uses a value of 2.
Let's reduce the N minimum to 2 and see what happens.
Cc: Bruno Prémont <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Tested-by: Bruno Prémont <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions