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| author | Manivannan Sadhasivam <[email protected]> | 2022-11-02 13:48:35 +0530 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2022-11-10 12:45:46 +0530 |
| commit | 883aebf6e1ea88145d64dcf940dbcb5181313338 (patch) | |
| tree | bcfa8821ebd18443e1c1956b53df1e57b5896d15 /tools/perf/scripts/python/bin | |
| parent | 9ddcd920f8edfe65c3670fbd0b49db00e1e562fe (diff) | |
phy: qcom-qmp-pcie: Fix sm8450_qmp_gen4x2_pcie_pcs_tbl[] register names
sm8450_qmp_gen4x2_pcie_pcs_tbl[] contains the init sequence for PCS
registers of QMP PHY v5.20. So use the v5.20 specific register names.
Only major change is the rename of PCS_EQ_CONFIG{2/3} registers to
PCS_EQ_CONFIG{4/5}.
Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions