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| author | Christophe Leroy <[email protected]> | 2021-06-03 08:41:40 +0000 |
|---|---|---|
| committer | Michael Ellerman <[email protected]> | 2021-06-17 00:09:08 +1000 |
| commit | 882136fb2f5208a35ddad9205b20e5791edd4782 (patch) | |
| tree | a3ee8083ebba9cd3a3c3ca4a200853c189a81a66 /tools/perf/scripts/python/bin | |
| parent | 863771a28e27dc9eaeaa88cea300370d032f0e0f (diff) | |
powerpc/32s: Simplify calculation of segment register content
segment register has VSID on bits 8-31.
Bits 4-7 are reserved, there is no requirement to set them to 0.
VSIDs are calculated from VSID of SR0 by adding 0x111.
Even with highest possible VSID which would be 0xFFFFF0,
adding 16 times 0x111 results in 0x1001100.
So, the reserved bits are never overflowed, no need to clear
the reserved bits after each calculation.
Signed-off-by: Christophe Leroy <[email protected]>
Signed-off-by: Michael Ellerman <[email protected]>
Link: https://lore.kernel.org/r/ddc1cfd2ec8f3b2395c6a4d7f2b0c1aa1b1e64fb.1622708530.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions