diff options
| author | Jan Kotas <[email protected]> | 2019-07-22 04:22:22 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <[email protected]> | 2019-07-25 06:43:01 -0400 |
| commit | 6ded416d4ac4ecbf104b897661cdfa2cdacf022a (patch) | |
| tree | 963e756610e111613fb267be99ba0f7e1fdc68bd /tools/perf/scripts/python/bin | |
| parent | bf9df90b3557ec6d5d92914da6a61453741d3e13 (diff) | |
media: Fix Lane mapping in Cadence CSI2TX
This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.
Signed-off-by: Jan Kotas <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Sakari Ailus <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions