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authorWenjing Liu <[email protected]>2024-04-29 12:11:05 -0400
committerAlex Deucher <[email protected]>2024-05-13 15:47:28 -0400
commit6ac05ae5fff84866a56358740681869c3bc62af3 (patch)
treec16de58daa8e19ddc688296290a8bd6e266c19c2 /tools/perf/scripts/python/bin
parent1dd50e634cb46880f3364ce629b09a37a5b3f888 (diff)
drm/amd/display: Allow higher DSC slice support for small timings on dcn401
[WHY] DML2.1 has added the support to determine ODM combine based on DSC slice count limitation. This support would allow us to support DSC slice higher than 4 on small timings. The change will allow higher DSC slice support independent from pixel clock in use. [HOW] Add a DCN401 get_enc_caps function to allow the support for DSC slice count higher than 4. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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