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authorGustavo Sousa <[email protected]>2024-03-12 13:36:35 -0300
committerLucas De Marchi <[email protected]>2024-03-13 05:46:45 -0700
commit66a0e0681392420b326f00ba732e6bda099eda29 (patch)
tree6d73db4e472f0e59f5123d04c0bf596feee1a30a /tools/perf/scripts/python/bin
parent452269e2f0ea180a4bc39fd4643df7fe2ea0bb8e (diff)
drm/i915: Extract intel_dbuf_mdclk_cdclk_ratio_update()
As of Xe2LPD, it is now possible to select the source of the MDCLK as either the CD2XCLK or the CDCLK PLL. Previous display IPs were hardcoded to use the CD2XCLK. For those, the ratio between MDCLK and CDCLK remained constant, namely 2. For Xe2LPD, when we select the CDCLK PLL as the source, the ratio will vary according to the squashing configuration (since the cd2x divisor is fixed for all supported configurations). To help the transition to supporting changes in the ratio, extract the function intel_dbuf_mdclk_cdclk_ratio_update() from the existing logic and call it using 2 as hardcoded ratio. Upcoming changes will use that function for updates in the ratio due to CDCLK changes. Bspec: 50057, 69445, 49213, 68868 Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
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