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| author | Manivannan Sadhasivam <[email protected]> | 2023-03-14 13:34:40 +0530 |
|---|---|---|
| committer | Bjorn Andersson <[email protected]> | 2023-03-15 15:17:22 -0700 |
| commit | 65d9975e5dae4601e8902765d08f55c246fd2022 (patch) | |
| tree | 5930a5197697b25af228cdd36373dd6db0bfe2d3 /tools/perf/scripts/python/bin | |
| parent | 413c8ecd48f1df8034c7b13881ded33b3d10171f (diff) | |
arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks
The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.
On SM6350, there is only one LLCC bank available. So let's just pass that
as "llcc0_base".
Reported-by: Parikshit Pareek <[email protected]>
Tested-by: Luca Weiss <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions