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| author | Jonathan Cameron <[email protected]> | 2022-05-08 18:55:54 +0100 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2022-06-14 11:53:12 +0100 |
| commit | 6268c6eebb13f228d418f9adaca848b3ed5b3cf9 (patch) | |
| tree | be9062dd3872ac7dcaa3eb38159211d55205be56 /tools/perf/scripts/python/bin | |
| parent | 58b74555afc8affe4ae4f57d396349158433fc80 (diff) | |
iio: adc: ad7606: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_ALIGN definition.
Update the comment to reflect the fact DMA safety 'may' require
separate cachelines.
Fixes: 7989b4bb23fe ("iio: adc: ad7616: Add support for AD7616 ADC")
Signed-off-by: Jonathan Cameron <[email protected]>
Acked-by: Nuno Sá <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin')
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