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authorFred <[email protected]>2023-02-23 20:04:50 +0800
committerUlf Hansson <[email protected]>2023-03-23 11:30:20 +0100
commit51dfc6142acecfea9bf2041ccadbc3438e31af56 (patch)
treebc3e15412aa9829cb05f988e072ebd2d04f277e5 /tools/perf/scripts/python/bin
parentca6b5fe277e91ebca5101dc00c0e26755f0ed6c4 (diff)
mmc: sdhci-pci-o2micro: Fix SDR50 mode timing issue
Change SDR50 mode clock source from DLL output clock to PLL open clock 1.HS200 and SDR104 mode select DLL output clock 2.SDR50 mode select PLL open clock Signed-off-by: Fred <[email protected]> Acked-by: Adrian Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
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