diff options
| author | Madhav Chauhan <[email protected]> | 2018-09-16 16:23:28 +0530 |
|---|---|---|
| committer | Jani Nikula <[email protected]> | 2018-09-26 15:52:26 +0300 |
| commit | 33868a91c1d9627b5003b8e299c46c6cfee4ff18 (patch) | |
| tree | c7fdd6798fdd4ea25272ac4672b4dc071159a68c /tools/perf/scripts/python/bin | |
| parent | 7a90938332d80faf973fbcffdf6e674e7b8f0914 (diff) | |
drm/i915/icl: Define data/clock lanes dphy timing registers
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
v2: Define mask/shift for bitfields and keep names as per BSPEC (Jani N)
Signed-off-by: Madhav Chauhan <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions