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authorAfzal Mohammed <[email protected]>2013-12-02 17:48:57 +0530
committerNishanth Menon <[email protected]>2014-05-05 14:34:37 -0500
commit27b7d5f3cc49f2e5cd6c005d73696058b7140c5c (patch)
treed8a8eb65bf9b001471aa4bddf87542683b07455e /tools/perf/scripts/python/bin
parent53a848be0a65c6fb105eb5ecb8b8b3edfa0f91ad (diff)
bus: omap_l3_noc: Add AM4372 interconnect error data
Add AM4372 information to handle L3 error. AM4372 has two clk domains 100f and 200s. Provide flagmux and data associated with it. NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware team, L3 timeout error cannot be cleared the normal way (by setting bit 31 in STDERRLOG_MAIN), instead it may be required to do system reset. L3 error handler can't help in such scenarios. Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as done for undocumented bits. Signed-off-by: Dave Gerlach <[email protected]> Signed-off-by: Afzal Mohammed <[email protected]> Signed-off-by: Sekhar Nori <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Acked-by: Santosh Shilimkar <[email protected]> Acked-by: Peter Ujfalusi <[email protected]> Tested-by: Darren Etheridge <[email protected]> Tested-by: Sekhar Nori <[email protected]>
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