diff options
| author | Mika Kuoppala <[email protected]> | 2012-10-29 16:59:26 +0200 |
|---|---|---|
| committer | Daniel Vetter <[email protected]> | 2012-11-11 23:51:09 +0100 |
| commit | 17f10fdc010254b8e9c0f1779abdaaee4757cabf (patch) | |
| tree | dc514c52a0091c6212afd2a9d188e45f706c733c /tools/perf/scripts/python/bin | |
| parent | 00c09d70df6b30c980f20facc1db3def3f5a637e (diff) | |
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:
commit 27c1cbd06a7620b354cbb363834f3bb8df4f410d
Author: Chris Wilson <[email protected]>
Date: Mon Apr 9 13:59:46 2012 +0100
drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g
Signed-off-by: Mika Kuoppala <[email protected]>
Signed-off-by: Daniel Vetter <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions