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authorMark Rutland <[email protected]>2018-07-05 15:16:49 +0100
committerWill Deacon <[email protected]>2018-07-05 17:24:13 +0100
commit1265132127b63502d34e0f58c8bdef3a4dc927c2 (patch)
tree93a9a6fa40fead74434716329786a15d721cd7dc /tools/perf/scripts/python/bin
parent25086263425641c74123f9387426c23072b299ea (diff)
arm64: don't zero DIT on signal return
Currently valid_user_regs() treats SPSR_ELx.DIT as a RES0 bit, causing it to be zeroed upon exception return, rather than preserved. Thus, code relying on DIT will not function as expected, and may expose an unexpected timing sidechannel. Let's remove DIT from the set of RES0 bits, such that it is preserved. At the same time, the related comment is updated to better describe the situation, and to take into account the most recent documentation of SPSR_ELx, in ARM DDI 0487C.a. Signed-off-by: Mark Rutland <[email protected]> Fixes: 7206dc93a58fb764 ("arm64: Expose Arm v8.4 features") Cc: Catalin Marinas <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Will Deacon <[email protected]> Signed-off-by: Will Deacon <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin')
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