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| author | Ville Syrjälä <[email protected]> | 2024-05-20 20:14:59 +0300 |
|---|---|---|
| committer | Ville Syrjälä <[email protected]> | 2024-05-22 15:45:34 +0300 |
| commit | 199bc8c175d712be1610dcad7f7240ad5c864281 (patch) | |
| tree | 9a824a7a03c8666ff6f5cece2c96c309cfc0a7a9 /tools/perf/scripts/python/bin/task-analyzer-record | |
| parent | 9cad70a9401f4d962e1baa9d607a291bfdc8f010 (diff) | |
drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
s/mtl+/tgl+/ as that's where this was introduced
Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
actually match the normal CUR_CTL register
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin/task-analyzer-record')
0 files changed, 0 insertions, 0 deletions