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authorKrzysztof Kozlowski <[email protected]>2021-09-20 15:25:59 +0200
committerRob Herring <[email protected]>2021-09-20 17:00:32 -0500
commitf46428f066dda4792760d2843f6b3addd0054ab7 (patch)
treee68a5529169254c7108198060fe9bb3af854a9e5 /tools/perf/scripts/python/bin/stackcollapse-report
parent6f4276ecc0f7c9eb4a6fa24f8c7c92ce527d0724 (diff)
dt-bindings: riscv: correct e51 and u54-mc CPU bindings
All existing boards with sifive,e51 and sifive,u54-mc use it on top of sifive,rocket0 compatible: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed: ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long Additional items are not allowed ('riscv' was unexpected) Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected) 'riscv' was expected Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
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