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authorMatt Roper <[email protected]>2019-12-12 16:15:09 -0800
committerMatt Roper <[email protected]>2019-12-13 12:06:34 -0800
commite8ab8d669d046a8e9b07707d2f00b9ba3e25d0ae (patch)
tree74c0237eaa4e4d91c06ece4fb3b7035fba160db5 /tools/perf/scripts/python/bin/stackcollapse-report
parent86ca2bf2f9d3941c0ee6087604a3f6cc3efd12ae (diff)
drm/i915/ehl: Define EHL powerwells independently of ICL
Outputs C and D on EHL are combo PHY outputs and thus should not be using the same TC AUX power well handlers as ICL. And even though icl_combo_phy_aux_power_well_ops works okay for EHL/JSL combo PHYs none of its special handling is actually necessary for this platform: * EHL/JSL don't actually need to program PORT_CL_DW12 * Display WA #1178 does not apply to EHL/JSL Thus we can simply drop back to using our standard "hsw-style" power well ops for EHL AUX power wells. Bspec: 4301 Fixes: f722b8c1e2a2 ("drm/i915/ehl: All EHL ports are combo phys") Cc: Jose Souza <[email protected]> Cc: Bob Paauwe <[email protected]> Cc: Vivek Kasireddy <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Lucas De Marchi <[email protected]>
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