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authorYongqiang Sun <[email protected]>2017-11-24 16:31:03 -0500
committerAlex Deucher <[email protected]>2017-12-14 11:00:35 -0500
commit904623ee5936e2226009b2f238f28781aecd2565 (patch)
treebba0b5b3e1634df87d77ba0949fc75742dd08bf9 /tools/perf/scripts/python/bin/stackcollapse-report
parent73da927b083737a8923c1bbc850274adffca1257 (diff)
drm/amd/display: Move wait for hpd ready out from edp power control.
It may take over 200ms for wait hpd ready. To optimize the resume time, we can power on eDP in init_hw, wait for hpd ready when doing link training. also create separate eDP enable function to make sure eDP is powered up before doing and DPCD access, as HPD low will result in DPDC transaction failure. After optimization, setpowerstate 145ms -> 9.8ms, DPMS 387ms -> 18.9ms Signed-off-by: Yongqiang Sun <[email protected]> Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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