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| author | Claudiu Beznea <[email protected]> | 2020-11-19 17:43:12 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2020-12-19 11:50:55 -0800 |
| commit | 8dc4af8bef127425271e06d09370a2479dae69c3 (patch) | |
| tree | 63114c00b05016b1744a70d8380db17e0e911087 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 0bb4623f13d46b2ea054777accff0c41af8036be (diff) | |
clk: at91: clk-sam9x60-pll: allow runtime changes for pll
Allow runtime frequency changes for PLLs registered with proper flags.
This is necessary for CPU PLL on SAMA7G5 which is used by DVFS.
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions