diff options
| author | Sowjanya Komatineni <[email protected]> | 2020-12-21 13:17:31 -0800 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2021-01-27 00:10:14 +0100 |
| commit | 88893986338beebcf5317bda80d43d4f6f7f7c7c (patch) | |
| tree | 6c5575ba3f087bd8e6f9e5afef8c837e3863b3bb /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 5c8fe583cce542aa0b84adc939ce85293de36e5e (diff) | |
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions