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| author | Geert Uytterhoeven <[email protected]> | 2016-01-16 15:17:36 +0100 |
|---|---|---|
| committer | Simon Horman <[email protected]> | 2016-02-05 10:43:42 +0100 |
| commit | 7b337e61a4104d5a0abde1e733916de2208800e6 (patch) | |
| tree | e3c0ceee12a7ad506f0c3d4418051462da32f9ec /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | a3fc85e27b7e3c29b30909929bc64737a19fd251 (diff) | |
arm64: dts: r8a7795: Add L2 cache-controller nodes
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Dirk Behme <[email protected]>
Signed-off-by: Simon Horman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions