diff options
| author | Matt Roper <[email protected]> | 2019-09-05 11:13:37 -0700 |
|---|---|---|
| committer | Matt Roper <[email protected]> | 2019-09-06 08:42:13 -0700 |
| commit | 71cd86cfaa12645ca39e5bbeceb2039af74fba2e (patch) | |
| tree | 2ab0eb651f8fca118e2b1016c42e4f114456a4c3 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | ca9cab183449787058f700fd0a74a8c91b277268 (diff) | |
drm/i915/tgl: Use refclk/2 as bypass frequency
Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
during some power state transitions.
Bspec: 49201
Cc: José Roberto de Souza <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Ville Syrjälä <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions