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| author | Amelie Delaunay <[email protected]> | 2021-01-05 10:05:23 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2021-01-13 20:40:21 +0530 |
| commit | 56bf858edd17bd4a320aca1a10aea7dbfb0c6699 (patch) | |
| tree | 7b862cb0233d2ec1af53f097e65434d19ae4d19e /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 04edf6d6e22b76aacb23d545a9fe642573f73c9b (diff) | |
phy: stm32: ensure pll is disabled before phys creation
To ensure a good balancing of regulators, force PLL disable either by
reset or by clearing the PLLEN bit.
If waiting the powerdown pulse delay isn't enough, return -EPROBE_DEFER
instead of polling the PLLEN bit, which will be low at the next probe.
Signed-off-by: Amelie Delaunay <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions