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| author | Animesh Manna <[email protected]> | 2023-11-08 12:53:02 +0530 |
|---|---|---|
| committer | Animesh Manna <[email protected]> | 2023-11-10 13:59:26 +0530 |
| commit | 3257e55d3ea7e35ea76ff6ae07347b803f068068 (patch) | |
| tree | ce3d94bf1aaf6e1a67293597a0666f998ffdbe17 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | cceeaa312d390e4f8407c056ae27ba7edd50307e (diff) | |
drm/i915/panelreplay: enable/disable panel replay
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Bspec: 1407940617
v1: Initial version.
v2:
- Use pr_* flags instead psr_* flags. [Jouni]
- Remove intel_dp_is_edp check as edp1.5 also has panel replay. [Jouni]
v3: Cover letter updated and selective fetch condition check is added
before updating its bit in PSR2_MAN_TRK_CTL register. [Jouni]
v4: Selective fetch related PSR2_MAN_TRK_CTL programmming dropped. [Jouni]
v5: Added PSR2_MAN_TRK_CTL programming as needed for Continuous Full
Frame (CFF) update.
v6: Rebased on latest.
Note: Initial plan is to enable panel replay in full-screen live active
frame update mode. In a incremental approach panel replay will be enabled
in selctive update mode if there is any gap in curent implementation.
Cc: Jouni Högander <[email protected]>
Cc: Arun R Murthy <[email protected]>
Cc: Jani Nikula <[email protected]>
Reviewed-by: Arun R Murthy <[email protected]>
Signed-off-by: Animesh Manna <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
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