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| author | Allen Yan <[email protected]> | 2017-10-13 11:01:53 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <[email protected]> | 2017-10-20 14:20:07 +0200 |
| commit | 30434b0713a5f4ecf00e9ffd3d47053882b1909a (patch) | |
| tree | 96983cebadafc50a4174d09c3742a515b15d89f6 /tools/perf/scripts/python/bin/stackcollapse-report | |
| parent | 2ff23c48028a77114757438f9a480c453f68d4b0 (diff) | |
serial: mvebu-uart: add TX interrupt trigger for pulse interrupts
Pulse interrupts (extended UART only) needs a change of state to trigger
the TX interrupt. In addition to enabling the TX_READY_INT_EN flag,
produce a FIFO state change from 'empty' to 'not full'. For this, write
only one data byte in TX start, making the TX FIFO not empty, and wait
for the TX interrupt to continue the transfer.
Signed-off-by: Allen Yan <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-report')
0 files changed, 0 insertions, 0 deletions